1. Field of the Invention
This invention relates generally to dynamic dual control on-die termination and more particularly to controlling on-die termination on a bi-directional, single ended data bus in high speed memory devices.
2. Description of the Related Art
When on-die termination is implemented by both the SRAM and Controller on a high-speed bi-directional data bus, bus contention must be avoided (as with any bi-directional data bus) without allowing the data bus to float (or be pulled) to the midpoint of the signal voltage swing.
Furthermore, the mechanism used to ensure that this requirement is met should not, ideally, require the addition of any control signals to the SRAM, and should be usable regardless of the Read and Write Latencies of the SRAM, and regardless of the transmission delay from Controller to SRAM (and SRAM to Controller).
FIG. 1 is a schematic diagram illustrating on-die termination on a bi-directional data signal between SRAM 140 and Controller 120. Synchronous SRAM is a Static Random Access Memory device having an input clock that is used to (1) Latch address, control, and write data signals driven to the SRAM 140, and (2) Control the output timing of read data signals driven from the SRAM 140. A Controller 120 is a component (e.g., an ASIC, FPGA, or other similar device) used to access the SRAM 140. The Controller initiates Write operations to store (write) data in the SRAM, and Read operations to retrieve (read) data from the SRAM.
A Bi-Directional Data Bus is a group of bi-directional transmission lines that is used by the Controller to both (1) Send multiple bits of write data, in parallel, to the SRAM during Write operations, and (2) Receive multiple bits of read data, in parallel, from the SRAM during Read operations. A Single-Ended Data Bus is a data bus where each data bit is associated with a single transmission line. In the described context, Common I/O (CIO) SRAM refers to a synchronous SRAM with a bi-directional, single-ended data bus.
Still referring to FIG. 1, a number of voltages are illustrated. VDDQ is the supply voltage used to power the SRAM 140 and Controller 120 I/O interfaces. VSS is the ground reference voltage used for the SRAM and Controller I/O interfaces. Typically, VSS=0V. VREF is the fixed reference voltage used by the SRAM and the Controller to control the switch point of a differential amplifier when it is used to receive a single-ended input signal. Typically, VREF is set to the mid-point of the input signal voltage swing—i.e., VDDQ/2 when the input signal swings from VSS (0V) to VDDQ nominally.
Differential amplifiers are electrical devices frequently used as an input receiver for receiving high-frequency single-ended input signals, as illustrated in FIG. 1. The differential amplifier has two inputs: “+” and “−”, and one output: “Y”. When the voltage applied to the “+’ input is greater than the voltage applied to the “−” input, the “Y” output is “high”. Conversely, when the voltage applied to the “+” input is less than the voltage applied to the “−” input, the “Y” output is “low”. When a differential amplifier is used to receive a single-ended input signal, the “+” input is connected to the input signal, and the “−” input is connected to VREF.
On-Die Termination (ODT) is an input termination that is implemented on-chip, on one or more input signals. By way of example, the on-die termination includes a pull-up device (or multiple devices, often transistors), connected between VDDQ and a particular input signal, and a pull-down device (or multiple devices, often transistors), connected between VSS and the same input signal. ODT controls and limits the voltage swing of the input signal, enabling higher-frequency data transmission between components than would otherwise be possible without ODT. With bi-directional data signals, ODT is implemented on each individual data input receiver in the SRAM 140, for receiving write data from the Controller 120, as well as on each individual data input receiver in the Controller, for receiving read data from the SRAM 140.
FIG. 2 is a table 200 illustrating an example of a CIO SRAM Clock Truth Table. A typical CIO SRAM has a clock input signal, which is often abbreviated as “K” or “CK”; multiple synchronous address input signals, often abbreviated “SA” (column 202); multiple Synchronous Data Input/Output signals, often abbreviated “DQ” (columns 208, 210); and two Synchronous Control Input signals, which are (1) Synchronous Enable, which is typically active “low”, often abbreviated “ LD” or “ SS” or “Ē” (column 204), and (2) Synchronous Read/Write Select, often abbreviated “R/ W” or “ SW” or “ W” (column 206).
In the Truth Table, (1) “1”=input “high”; “0”=input “low”; “V”=input “valid”; “X”=input “don't care”; (2) “High-Z” indicates that the DQ output driver is disabled; (3) “RL” refers to the “Read Latency” of the SRAM. That is, how many cycles it takes from when the SRAM detects a Read operation to when it begins to send read data to the Controller; and (4) “WL” refers to the “Write Latency” of the SRAM. That is, how many cycles it takes from when the SRAM detects a Write operation to when it begins to sample write data from the Controller.
When the SRAM samples Synchronous Enable “high”, it executes a NOP operation (i.e., neither a Read nor a Write operation), regardless of the state of Synchronous Read/Write Select. When the SRAM samples Synchronous Enable “low”, it executes a Read operation if it samples Synchronous Read/Write Select “high”, or a Write operation if it samples Synchronous Read/Write Select “low”.
There is a problem when a bi-directional bus is utilized in configurations such as that described above. Because a bi-directional bus is utilized for data transmission, the SRAM should at a minimum (1) have its DQ input termination fully enabled before it begins receiving data on the bus, and kept fully enabled until after it has finished receiving data on the bus; and (2) Have its DQ input termination fully disabled while driving data on the bus. The Controller must also do the same.
During this enable/disable process, a condition may arise where both the SRAM and Controller have disabled their DQ output drivers, and one (or both) of them has enabled its DQ input termination. If this occurs, and the pull-up and pull-down termination impedances are the same, the DQs will be pulled to VDDQ/2=VREF by the input termination. This situation (i.e., DQ steady-state voltage=VREF) must be avoided, because it can cause the differential amplifier to enter a meta-stable state, resulting in high current and potential electrical damage to the components.
What is needed is enabling and disabling DQ input termination in a CIO SRAM (and in the Controller as well) in such a way that the DQs are not pulled to VREF under circumstances such as those described above.